Jasnoor Sandhu | Detailed CV

Professional Profile

Electronics and communication engineer from IIT (BHU) with a Computer Science minor and production R&D experience at Siemens EDA. Works at the hardware–software boundary across inter-process communication, emulation runtimes, Linux systems, RTL and FPGA development. Progressed from a Siemens hardware internship to a full-time software engineering role; also contributed to compiler research at EPFL and ROS2 robotics research at Victoria University. Brings strong systems debugging, structured experimentation and a record of converting technical investigations into reliable engineering outcomes.

Technical Expertise

Languages: C, C++, Python, Verilog, SystemVerilog, Linux Shell, Perl

Systems: Linux, IPC, OS/kernel concepts, runtime debugging, data structures, OOP

Digital/FPGA: RTL design, AXI Stream, FPGA prototyping, simulation, verification

Tools: Xilinx Vivado/Vitis, MATLAB, Proteus, PYNQ-Z1, Questa, Veloce

Professional Experience

Software Engineer, TBX (TestBench-Express) · Siemens EDA

07 Jul 2025 – Present
Noida, India

Research & Development · Veloce hardware-emulation platform

Maintain and extend TBX-IPC, the inter-process communication layer supporting coordination across the TestBench-Express runtime.
Delivered the tbx-session-id initiative to strengthen session identification and improve the operational stability of the Veloce platform.
Investigate platform and runtime behavior across IPC boundaries, building practical depth in Linux OS, kernel-facing behavior and emulation runtime internals while working on the newest chiplet flow of Veloce.
Contribute to Questa runtime work alongside core TBX responsibilities, diagnosing issues that span simulation, emulation and systems software.
Apply production-codebase discipline to maintenance, debugging and reliability improvements within a complex EDA platform.

Hardware Engineering Intern · Siemens EDA

Summer 2024
Noida, India

Internship performance led to a full-time offer and return to Siemens EDA.

Re-engineered a C++ utility to detect faulty flip-flops caused by compiler issues or emulation errors, reducing analysis time by 50%.
Added progress reporting, flop filtering and waveform visualisation, making investigations faster and easier for users; the enhanced utility was adopted by multiple team members.
Built a systems foundation across Linux, OS and emulation through shell work and large-codebase debugging, alongside exposure to production R&D on Veloce and Questa runtimes.

Research, education & leadership

A cross-disciplinary engineering foundation

Research Experience

Summer Research Intern · EPFL, Laboratory for Processor Architecture

Summer 2025
Lausanne, Switzerland

Dynamatic High-Level Synthesis compiler · Supervised by Prof. Paolo Ienne

Improved Dynamatic’s buffer-placement workflow for dataflow circuits, with emphasis on mixed-integer linear programming (MILP)-based scheduling.
Identified missing throughput constraints and corrected the formulation, improving the accuracy of buffer insertion.
Worked at the intersection of compiler optimization and digital hardware, reasoning about scheduling, throughput and dataflow behavior.

Research Intern · Victoria University

Summer 2023
Melbourne, Australia

ROS2 robotics · TurtleBot4 · Raspberry Pi 4 · Linux

Modified ROS2 packages supporting TurtleBot4 navigation and mapping in a Raspberry Pi 4/Linux environment.
Integrated and tested software within a physical robotics stack, building practical experience with distributed robotic systems.
Planned and delivered a live TurtleBot4 demonstration for 40+ university students.

Education

Indian Institute of Technology (BHU), Varanasi

B.Tech., Electronics & Communication Engineering · 2021–2025

Minor: Computer Science Engineering

CGPA: 9.50/10 · Department Rank: 3/146

Sudesh Vatika Convent School

Senior Secondary (Class XII) · 2021

91.6%

St. Joseph’s High School

Secondary (Class X) · 2019

92.5%

Leadership

Joint General Secretary

2024

Electronics Engineering Society, IIT (BHU)

Coordinated Marketing, Design, Web, Publicity and PR teams for EES Fest’24.
Helped deliver the festival for a total footfall of 800 students.

Event Manager, RoboWars

Technex’24

Coordinated 24 robot-war teams, built the arena, and managed event logistics for 1,000 attendees.

DUGC Representative

3 years

Selected for three consecutive years as DUGC Representative, coordinating with faculty and representing student perspectives in departmental academic matters.

Selected Honours & Distinctions

Gold Medal, IIT (BHU): Recognised for exceptional academic performance; Department Rank 3/146.
JEE Advanced 2021: All India Rank 2321.
JEE Main 2021: 99.24 percentile.

CryptX, Prastuti’22: 2nd place in a cryptography event at IIT (BHU).
Innovation Quest: 2nd place in a team research event on alternatives to lithium-ion batteries.

Engineering range

Systems software: IPC, Linux and emulation runtime work in a production EDA platform.

Hardware design: RTL, AXI Stream IP, FPGA prototyping and numerical validation.

Research: HLS compiler scheduling, wireless waveform simulation and ROS2 robotics.

Selected technical portfolio

Projects

FPGA IP

Goldschmidt Division Algorithm IP

Designed a SystemVerilog floating-point division IP around the multiplication-based Goldschmidt algorithm and exposed it through an AXI Stream interface for integration in a Vivado block design.

Integrated and validated the design on a PYNQ-Z1 board, achieving six-cycle division with 99.99% accuracy.

github.com/jasnoor-sandhu/GoldSmithDiv

SystemVerilog · AXI Stream · Vivado/Vitis · PYNQ-Z1 · RTL verification

OTFS

OTFS Waveform Design for Next-Generation Wireless

Built MATLAB simulations comparing OFDM and OTFS across signal-to-noise conditions, with emphasis on robustness in high-mobility, high-Doppler channels.

Measured a 20% improvement in spectral efficiency and a 30% BER improvement in low-SNR scenarios; extended the work toward FPGA-oriented OTFS exploration.

github.com/jasnoor-sandhu/OTFS-OFDM · OTFS-PYNQ-FPGA

MATLAB · OTFS/OFDM · BER analysis · Signal processing · FPGA exploration

FPGA DSP
Acceleration

FIR Filter on PYNQ-Z1

Implemented a five-tap FIR filter as a programmable-logic accelerator and compared it with a processor-side software implementation using the same signal-processing workload.

Configured coefficients for 5 dB and −40 dB attenuation targets and recorded approximately 7× hardware acceleration.

github.com/jasnoor-sandhu/FIR-Filter-PYNQ-FPGA

VHDL · PYNQ-Z1 · FIR filtering · Python · Matplotlib · Hardware acceleration

FPGA DSP
Design Flow

1024-Point FFT on PYNQ-Z1

Built and exercised a 1024-point FFT hardware design in Xilinx Vivado 19.2, using a PYNQ overlay, DMA transfers and allocated complex-valued buffers.

Generated multi-tone test data, compared programmable-logic output with NumPy FFT results and visualized numerical error to validate the hardware/software design flow.

github.com/jasnoor-sandhu/FFT-PYNQ-FPGA

VHDL · FFT · DMA · PYNQ overlay · NumPy · Vivado

RTL Design

Bubble Sort in RTL

Translated nested-loop compare-and-swap behavior into an explicit data-flow model and finite-state machine, then implemented and simulated the sorter in Verilog.

Used Vivado waveform verification to reason about register updates, clocked state transitions and hardware realization of a software algorithm.

github.com/jasnoor-sandhu/Bubblesort_vhdl

Verilog · RTL · FSM design · Vivado · Simulation