Project
Bubble Sort in RTL
A foundational RTL implementation of the Bubble Sort algorithm
Overview
Translating a software algorithm into hardware
Bubble Sort is a simple algorithm to reason about in software, but implementing it in RTL forces you to think explicitly about state, timing, and data movement between registers — there's no implicit call stack or loop to lean on.
This was one of my earliest RTL projects: I created a data flow model and a state diagram for the Bubble Sort algorithm, then implemented and simulated it in Verilog using Vivado.
Approach
State machines, not loops
The core challenge was re-expressing the nested-loop compare-and-swap logic of Bubble Sort as an explicit finite state machine driving register updates on each clock cycle.
Data flow modeling → state diagram design → Verilog implementation → simulation & waveform verification in Vivado
Working through this project built my foundational understanding of sorting algorithms translated to hardware, RTL design discipline, and how to verify correctness through simulation rather than just reading code.
Outcomes
A grounding in RTL fundamentals
This project was a stepping stone toward the more advanced FPGA and IP-design work I've done since (like the Goldschmidt Division IP) — it's where I first got comfortable thinking in registers, clocks, and state transitions instead of sequential code.
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