Project
Goldsmith Division Algorithm IP
A hardware IP block for fast, high-accuracy floating-point division
Overview
A custom IP for fast division on FPGA
The Goldschmidt division algorithm computes division iteratively using multiplication, making it well suited to pipelined hardware implementations where a direct divider would be slow or resource heavy.
I designed and implemented an IP block for the Goldschmidt Division Algorithm using an AXI Stream interface, so it could be dropped into a larger Vivado block design as a standard streaming component.
The IP was integrated and tested end-to-end on a Pynq Z1 FPGA board, validating both the numerical approach and the hardware interface under real timing constraints.
Approach
Iterative refinement, pipelined in hardware
Rather than a slow restoring/non-restoring division circuit, the Goldschmidt method converges to the quotient through repeated multiply-and-refine steps — a good fit for a pipelined datapath.
Operand setup → iterative refinement → convergence check → AXI Stream output
The design streams operands in and results out over AXI Stream, which made it straightforward to integrate as a block in a larger Vivado IP-integrator design rather than a bespoke point-to-point interface.
Outcomes
Fast and accurate in hardware
6 cycles
Floating-point division latency
99.99%
Accuracy achieved
Pynq Z1
FPGA board used for validation
AXI Stream
Interface protocol
The final implementation achieved floating-point division in just 6 cycles with 99.99% accuracy — demonstrating that an iterative, multiplication-based approach can match dedicated divider hardware in both speed and precision on real FPGA fabric.
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